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PRELIMINARY DATA SHEET
MICRONAS
CDC1607F-E Automotive Controller
Edition May 26, 2004 6251-608-1PD
MICRONAS
CDC1607F-E
Contents Page 3 3 7 9 9 10 11 12 12 13 14 15 16 17 17 19 19 20 22 Section 1. 1.1. 1.2. 2. 2.1. 2.2. 2.3. 3. 3.1. 3.2. 3.3. 3.4. 4. 5. 5.1. 6. 6.1. 7. 8. Title Introduction Features Abbreviations Package and Pins Package Outline Dimensions Pin Assignment External Components Electrical Data Absolute Maximum Ratings Recommended Operating Conditions Characteristics Recommended Quartz Crystal Characteristics CPU, RAM, ROM and Banking Core Logic Control Register CR Hardware Options Functional Description Differences Data Sheet History
PRELIMINARY DATA SHEET
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Micronas
1. Introduction
Release Note: Revision bars indicate significant changes to the previous edition. The IC is a single-chip controller for use in automotive applications. The CPU on the chip is an upgrade of the 65C02 with 16-bit internal data and 24-bit address bus. The chip consists of timer/counters, an interrupt controller, a multichannel A/D converter, a stepper motor and LCD driver, CAN interfaces and PWM outputs. This document provides MCM Flash hardware-specific information. General information on operating the IC can be found in the document "CDC16xxF-E Automotive Controller - Family User Manual, CDC1605F-E Automotive Controller Specification" (6251-606-1PD).
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May 26, 2004; 6251-608-1PD
PRELIMINARY DATA SHEET
1.1. Features
Table 1-1: CDC16xxF Family Feature List This Document: Item Core CPU CPU-Active Operation Modes Power-Saving Modes (CPU Inactive) EMI Reduction Mode Oscillators RAM ROM 16-bit 65C816, featuring software compatibility with its 8-bit NMOS and CMOS 6500-series predecessors FAST, SLOW and DEEP SLOW WAKE and IDLE selectable in FAST mode 4 to 12 MHz Quartz and 20 to 57 kHz internal RC 6 KB ROMless, external program storage with up to 16 MB, internal 2 KB Boot ROM 256 KB Flash, bottom boot configuration, internal 2 KB Boot ROM 2 KB 64 KB 4 MHz to 12 MHz Quartz FAST and SLOW CDC1605F-E EMU CDC1607F-E MCM Flash CDC1631F-E MASK ROM CDC1605F-C EMU CDC1607F-C MCM Flash CDC1641F-C Mask ROM CDC1652F-C Mask ROM CDC1672F-C Mask ROM
CDC1607F-E
6 KB ROMless, external program storage with up to 16 MB, internal 2 KB Boot ROM 256 KB Flash, bottom boot configuration, internal 2 KB Boot ROM
2.75 KB 90 KB
4 KB 128 KB
6 KB 216 KB
3
Table 1-1: CDC16xxF Family Feature List, continued This Document: Item Multiplier, 8 by 8 bit Digital Watchdog Central Clock Divider Interrupt Controller expanding NMI Port Interrupts including Slope Selection CDC1605F-E EMU 16 inputs,15 priority levels 4 inputs 10 CDC1607F-E MCM Flash CDC1631F-E MASK ROM CDC1605F-C EMU CDC1607F-C MCM Flash CDC1641F-C Mask ROM CDC1652F-C Mask ROM CDC1672F-C Mask ROM
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CDC1607F-E
Port Wake-Up Inputs including Slope / Level Selection Patch Module Boot System
10 ROM locations allows in-system downloading of code and data into RAM via serial link
5 ROM locations -
10 ROM locations allows in-system downloading of code and data into RAM via serial link
5 ROM locations -
6 ROM locations -
Analog Reset/Alarm Clock and Supply Supervision 10-bit ADC, charge balance type ADC Reference Comparators LCD Combined Input for Regulator Input Supervision
PRELIMINARY DATA SHEET
9 channels (5 channels selectable as digital input) VREF Pin P06COMP with 1/2 AVDD reference Internal processing of all analog voltages for the LCD driver
Micronas
Table 1-1: CDC16xxF Family Feature List, continued This Document: Item Communication DMA UART Synchronous Serial Peripheral Interfaces Full CAN modules V2.0B 1 DMA Channel for serving the Graphics Bus interface 3: UART0, UART1 and UART2 2: SPI0 and SPI1 3: CAN0, CAN1 and CAN2 with 256-byte object RAM each (LCAN000F) 1 master module 1: UART0 1: SPI0 1: CAN0 with 256-byte object RAM (LCAN000F) 1 DMA Channel for serving the Graphics Bus interface 3: UART0, UART1 and UART2 2: SPI0 and SPI1 3: CAN0, CAN1 and CAN2 with 256-byte object RAM each (LCAN0009) 1 master module 1: UART0 1: SPI0 1: CAN0 with 256-byte object RAM (LCAN0009) 1 DMA Channel for serving the Graphics Bus interface 3: UART0, UART1 and UART2 2: SPI0 and SPI1 2: CAN0 and CAN1 with 256-byte object RAM each (LCAN0009) CDC1605F-E EMU CDC1607F-E MCM Flash CDC1631F-E MASK ROM CDC1605F-C EMU CDC1607F-C MCM Flash CDC1641F-C Mask ROM CDC1652F-C Mask ROM CDC1672F-C Mask ROM
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May 26, 2004; 6251-608-1PD
PRELIMINARY DATA SHEET
DIGITbus Input & Output Universal Ports selectable as 4:1 mux LCD Segment/Backplane lines or Digital I/O Ports Universal Port Slew Rate Stepper Motor Control Modules with High-Current Ports 8-bit PWM Modules
1 master module
up to 52 I/O or 48 LCD segment lines (=192 segments), in groups of two, configurable as I/O or LCD
HW preselectable 5 Modules, 24 dI/dt controlled ports
5 Modules: PWM0, PWM1, PWM2, PWM3 and PWM4 2
3 Modules: PWM0, PWM1, PWM2
5 Modules: PWM0, PWM1, PWM2, PWM3 and PWM4
2 Modules: PWM0, PWM1
5 Modules: PWM0, PWM1, PWM2, PWM3 and PWM4
CDC1607F-E
Audio Module with autodecay SW selectable Clock outputs
5
Table 1-1: CDC16xxF Family Feature List, continued This Document: Item Polling / Flash Timer Output Timers & Counters 16-bit free running counters with Capture/ Compare modules 16-bit timers 8-bit timers Real Time Clock, Delivering Hours, Minutes and Seconds Miscellaneous Scalable layout in CAN, RAM and ROM Various randomly selectable HW options Mask programmed according to user specification CCC0 with 3CAPCOM CDC1605F-E EMU CDC1607F-E MCM Flash CDC1631F-E MASK ROM CDC1605F-C EMU CDC1607F-C MCM Flash CDC1641F-C Mask ROM CDC1652F-C Mask ROM CDC1672F-C Mask ROM
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CDC1607F-E
1 High-Current Port output operable in Power-Saving Mode
1: T0 2: T1 and T2 -
Most options SW programmable, copy from user program storage during system start-up
Most options SW programmable, copy from user program storage during system start-up
Core Bond-Out Supply Voltage Temperature Range Package Type
4.5 V to 5.5 V Tcase: 0 C to +70 C
-
-
PRELIMINARY DATA SHEET
Tcase: -40 C to +105 C
Tamb: -40 C to +85 C
Ceramic 177PGA 176
Plastic 100QFP 0.65mm pitch 100
Ceramic 177PGA 176
Plastic 100QFP 0.65mm pitch 100
Micronas
Bonded Pins
1.2. Abbreviations
AM CAN CAPCOM CPU DMA ERM IR LCD P06COMP PINT PSM PWM RTC SM SPI T0 T1, T2 UART Audio Module Controller Area Network Module Capture/Compare Module Central Processing Unit Direct Memory Access Module EMI Reduction Module Interrupt Controller Liquid Crystal Display Module P0.6 Alarm Comparator Port Interrupt Module Power-Saving Module 8-Bit Pulse Width Modulator Module Real-time Clock Stepper Motor Control Module Serial Synchronous Peripheral Interface 16-Bit Timer 0 8-Bit Timers 1 and 2 Universal Asynchronous Receiver Transmitter
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PRELIMINARY DATA SHEET
CDC1607F-E
7
CDC1607F-E
PRELIMINARY DATA SHEET
VSS VDD
UVDD UVSS UPort1
LCD Control CAN 1 Reset/Alarm Test RESETQ TEST XTAL1 XTAL2 Watchdog Clock ERM RC Oscillator RTC Power Saving Module 16 Inputs Interrupt Controller 65C816 CPU 8-Bit Timer 2 16-Bit CAPCOM 1 16-Bit CAPCOM 2 16-Bit Timer 0 DIGITbus Audio Module Banking 8-Bit Timer 1 Patch Module
8
UPort2
DMA Logic
8
UPort3
8
Multiplier 8 by 8 bit
UART 0 UART 2
UPort4
VREF AVDD AVSS PPort0
SRAM 6k x 8
8
9
10-Bit ADC
CAN 2
Clock Out 0 HPort0 6 Flash 256k x 8 Clock Out 1 16-Bit CAPCOM 0 UART 1 UPort5 Stepper Motor Control
8
HPort1
6
8-Bit PWM 2 8-Bit PWM 0
HPort2
Boot ROM 8-Bit PWM 4
CAN 0 SPI 0 SPI 1
UPort6
8
6
HPort3
UPort7
6
8-Bit PWM 1 8-Bit PWM 3
4
HVDD1 HVSS1 HVDD2 HVSS2
Fig. 1-1: Block diagram of CDC1607F-E
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PRELIMINARY DATA SHEET
CDC1607F-E
2. Package and Pins
2.1. Package Outline Dimensions
Fig. 2-1: PMQFP100-1: Plastic Metric Quad Flat Package, 100 leads, 14 x 20 x 2.7 mm3 Ordering code: QB Weight approximately 1.7 g
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CDC1607F-E
2.2. Pin Assignment
Pin Functions Port Port Special Out Special In GWRQ GRDQ Pin No. 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin No. 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PRELIMINARY DATA SHEET
Bus Mode
LCD Mode SEG7.3 SEG7.2 SEG7.1 SEG7.0
ADB7 ADB6 ADB5 ADB4 ADB3 ADB2 ADB1 ADB0
SEG3.7 T2-OUT SEG3.6 CC1-OUT SEG3.5 SPI1-CLK-OUT SEG3.4 T0-OUT SEG3.3 CC2-OUT SEG3.2 DIGIT-OUT SEG3.1 CO1 SEG3.0 SPI1-D-OUT SEG6.7 CAN0-TX SEG6.6 PINT1-OUT SEG6.5 T1-OUT SEG6.4 SPI0-D-OUT
SPI1-CLK-IN WP0 DIGIT-IN SPI1-D-IN MULTI-TEST-IN CAN0-RX/WP1 SPI0-D-IN
SEG6.3 SEG6.2 SEG6.1 SEG6.0 WEQ SEG1.7 CEQ SEG1.6 ITSTOUT SEG1.5 RWQ SEG1.4 PH2 BP3 OEQ BP2 BE BP1 RDY BP0 STOPCLK VPQ VPA VDA DB7 DB6
SPI0-CLK-OUT T1-OUT LCD-CLK-OUT LCD-SYNC-OUT CAN1-TX LCD-CLK-OUT LCD-SYNC-OUT
SPI0-CLK-IN PINT2-IN/WP5 PINT1-IN/WP4 PINT0-IN/WP3 CAN1-RX/WP2
ITSTOUT SMB1+ SMB1SMB2+ SMB2SME1+/PWM2 SME1-/PWM0
SMB-COMP
DB5 DB4 DB3 DB2 DB1 DB0
SME2+ SME2SMA1+ SMA1SMA2+ SMA2-
SME-COMP
SMA-COMP
Basic Function U7.3 U7.2 U7.1 U7.0 UVSS UVDD U3.7 U3.6 U3.5 U3.4 U3.3 U3.2 U3.1 U3.0 U6.7 U6.6 U6.5 U6.4 TEST RESETQ XTAL2 XTAL1 VSS VDD U6.3 U6.2 U6.1 U6.0 U1.7 U1.6 U1.5 U1.4 U1.3 U1.2 U1.1 U1.0 H1.5 H1.4 H1.3 H1.2 H1.1 H1.0 HVDD1 HVSS1 H0.5 H0.4 H0.3 H0.2 H0.1 H0.0
100 1
91 90
81 80
30 31 40 41 50
51
NC = not connected, leave vacant
Basic Function U4.0 U4.1 U4.2 U4.3 U4.4 U4.5 U4.6 U4.7 U5.0 U5.1 U5.2 U5.3 U5.4 U5.5 U5.6 U5.7 U2.0/GD0 U2.1/GD1 U2.2/GD2 U2.3/GD3 U2.4/GD4 U2.5/GD5 U2.6/GD6 U2.7/GD7 AVSS AVDD VREF P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.8 P0.9 H2.0 H2.1 H2.2 H2.3 H2.4 H2.5/Pol HVSS2 HVDD2 H3.0 H3.1 H3.2 H3.3 H3.4 H3.5
Pin Functions Port Port Special In Special Out CAN2-RX/WP7 CAN2-TX UART2-RX UART2-TX UART0-RX/WP8 UART0-TX CC2-IN CC1-OUT CC1-IN CC0-IN CO1 INT-TEST-IN CC0-OUT LCD-CLK-IN AM-PWM LCD-SYNC-IN AM-OUT IRQ UART1-TX ABORTQ CO0 PINT3/WP6 PWM2 PINT3/UART1-RX PINT0-OUT
LCD Mode SEG4.0 SEG4.1 SEG4.2 SEG4.3 SEG4.4 SEG4.5 SEG4.6 SEG4.7 SEG5.0 SEG5.1 SEG5.2 SEG5.3 SEG5.4 SEG5.5 SEG5.6 SEG5.7 SEG2.0 SEG2.1 SEG2.2 SEG2.3 SEG2.4 SEG2.5 SEG2.6 SEG2.7
Bus Mode ADB8 ADB9 ADB10 ADB11 ADB12 ADB13 ADB14 ADB15
ADB16 ADB17 ADB18 ADB19 ADB20 ADB21 ADB22 ADB23
P0.1 digital input P0.2 digital input P0.3 digital input P0.4 digital input P0.5 digital input P0.6 Compar. inp.
SMC-COMP
WP9
SMC2SMC2+ SMC1SMC1+ PWM0 PWM4
SMD-COMP
PWM1 PWM3 SMD2SMD2+ SMD1SMD1+
Fig. 2-2: Pin Assignment for PMQFP100-1 Package
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PRELIMINARY DATA SHEET
CDC1607F-E
2.3. External Components
+5 V L
UVDD
VDD C = 100 n to 150 n C VSS 18 p C XTAL1 HVSS 0 to 1 HVDD 0 to 1 2*C C = 100 n to 150 n +5 V
System Ground
+5 V Analog
IC
AVDD +5 V 18 p 4.7 k 47 n XTAL2 VREF 10 n C
Resetq System Ground
RESETQ
UVSS
AVSS
Analog Ground
Fig. 2-3: Recommended external supply and quartz connection for low electromagnetic interference (EMI) To provide effective decoupling and to improve EMC behavior, the small decoupling capacitors must be located as close to the supply pins as possible. The self-inductance of these capacitors and the parasitic inductance and capacitance of the interconnecting traces determine the self-resonant frequency of the decoupling network. A frequency too low will reduce decoupling effectiveness, increase RF emissions and may affect device operation adversely. XTAL1 and XTAL2 quartz connections are especially sensitive to capacitive coupling from other PC board signals. It is strongly recommended to place quartz and oscillation capacitors as close to the pins as possible and to shield the XTAL1 and XTAL2 traces from other signals by embedding them in a VSS trace. The RESETQ pin adjacent to XTAL2 should be supplied with a 47 nF capacitor, to prevent fast RESETQ transients from being coupled into XTAL2, to prevent XTAL2 from coupling into RESETQ, and to guarantee a time constant of 200 s, sufficient for proper Wake Reset functionality.
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CDC1607F-E
3. Electrical Data
PRELIMINARY DATA SHEET
3.1. Absolute Maximum Ratings
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute maximum ratings conditions for extended periods will affect device reliability. This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than absolute maximum-rated voltages to this high-impedance circuit. Table 3-1: All voltages listed are referenced to ground (UVSS=HVSSn=AVSS=0V), except where noted. All ground pins except VSS must be connected to a low-resistive ground plane close to the IC. Symbol VSUP Parameter Core Supply Voltage Port Supply Voltage Analog Supply Voltage SM Supply Voltage 1 SM Supply Voltage 2 Voltage Difference between VDD and AVDD, resp. UVDD Core Supply Current Port Supply Current Analog Supply Current SM Supply Current @Tj=105 C, Duty Factor = 0.71 1) Input Voltage Pin Name VDD UVDD AVDD HVDD1 HVDD2 VDD, AVDD UVDD VDD, VSS UVDD, UVSS AVDD, AVSS HVDD1, HVSS1 HVDD2, HVSS2 U-Ports, XTAL,RESETQ, TEST P0-Ports VREF H-Ports Iin Io Input Current Output Current all Inputs U-Ports H-Ports toshsl Tj Ts Pmax
1) This
Min. -0.3
Max. 6.0
Unit V
VDD ISUP IASUP IHSUP Vin
-0.5 -100 -20 -380 UVSS-0.5
0.5 100 20 380 UVDD+0.7
V mA mA mA V
UVSS-0.5 HVSS-0.5 0 -5 -60
AVDD+0.7 HVDD+0.7 2 5 60 indefinite
V V mA mA mA s C C W
Duration of Short Circuit in Port SLOW Mode to UVSS or UVDD Junction Temperature under Bias Storage Temperature Maximum Power Dissipation
U-Ports except U3.2 in DP Mode -45 -45
115 125 0.8
condition represents the worst case load with regard to the intended application.
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PRELIMINARY DATA SHEET
CDC1607F-E
3.2. Recommended Operating Conditions
Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. Keep UVDD=AVDD during all power-up and power-down sequences. Functional operation of the device beyond those indicated in the "Recommended Operating Conditions/Characteristics" is not implied and may result in unpredictable behavior, reduce reliability and lifetime of the device. Table 3-2: All voltages listed are referenced to ground (UVSS=HVSSn=AVSS=0V), except where noted. All ground pins except VSS must be connected to a low-resistive ground plane close to the IC . Symbol VDD Parameter Supply Voltage Port Supply Voltage Analog Supply Voltage SM Supply Voltage 1 SM Supply Voltage 2 Voltage Difference between VDD and AVDD resp. UVDD AVDD Ripple, Peak-to-Peak XTAL Clock Frequency XTAL Clock Frequency using ERM Vil Low Input Voltage Pin Name VDD UVDD AVDD HVDD1 HVDD2 VDD, AVDD UVDD AVDD XTAL1 XTAL1 U-Ports H-Ports P0-Ports TEST U-Ports H-Ports P0-Ports TEST RESETQ RESETQ 0.86*VDD 4 4 Min. 4.5 Typ. 5 Max. 5.5 Unit V
HVDD VDD dAVDD fXTAL
4.75 -0.2
5
5.25 0.2 200 12 10 0.51*VDD
V V mV MHz MHz V
Vih
High Input Voltage
V
RVil WRVil
Reset Active Input Voltage Reset Active Input Voltage during Power-Saving Modes and Wake Reset Reset Inactive and Alarm Active Input Voltage Reset Inactive and Alarm Inactive Input Voltage Reset Inactive during Power-Saving Modes ADC Reference Input Voltage P0 ADC Input Port Input Voltage
0.9 0.6
V V
RVim RVih WRVih VREFi P0Vi
RESETQ RESETQ RESETQ VREF P0-Ports
1.6 2.9 UVDD - 0.4V 2.56 0
2.1
V V V
AVDD VREFi
V V
Clock Input from External Generator XVil XVih DXTAL Clock Input Low Voltage Clock Input High Voltage Clock Input High-to-Low Ratio XTAL1 XTAL1 XTAL1 0.8*VDD 0.45 0.55 0.2*VDD V V
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CDC1607F-E
3.3. Characteristics
PRELIMINARY DATA SHEET
Listed are only those characteristics that differ from Chapter 3.3 of Document "CDC16xxF-E Automotive Controller - Family User Manual, CDC1605F-E Automotive Controller Specification" (6251-606-1PD). All not differing characteristics, that are not listed here, apply, but in a TCASE temperature range extended to -40 C to +105 C. Table 3-3: UVSS = HVSS1 = HVSS2 = AVSS = 0 V, 4.5 V < VDD = AVDD = UVDD < 5.5 V, 4.75 V < HVDD1 = HVDD2 < 5.25 V, TCASE = -40 C to +105 C, fXTAL = 10 MHz Symbol Package Rthjc Rthja Thermal Resistance from Junction to Case Thermal Resistance from Junction to Ambient 9 31 C/W C/W measured on Micronas typical 2-layer board, 1s1p, described in document "Integrated Circuits - Thermal Characterization of Packages" (6200266-1E) (modified JESD-51.3) CMOS levels on all Inputs, no Loads on Outputs, difference between any two VDDs within 0.2 V VDD 35 45 IDDS VDD SLOW Mode Supply Current VDD 1.5 65 85 2.0 mA mA mA Flash Read 3) Flash Write/Erase 3) all Modules OFF 2), 3) all clocks disabled by hardware option settings all Modules OFF 2), 3) all hardware options set to their RESET values all Modules OFF 2), 3) all hardware options set to their RESET values fxtal = 4 MHz 3) fxtal = 10 MHz 3) internal RC oscill. Parameter Pin Na. Min. Typ. 1) Max. Unit Test Conditions
Supply Currents
IDDF
VDD FAST Mode Supply Current
2.5
3.5
mA
IDDD
VDD DEEP SLOW Mode Supply Current VDD IDLE Mode Supply Current
VDD
0.75
1.0
mA
IDDI
VDD
70 180 12
135 260 55 50 0.3
A A A A mA mA mA
IDDW UIDDa AIDDa
VDD WAKE Mode Supply Current UVDD Active Supply Current AVDD Active Supply Current
VDD UVDD AVDD
1
no Output Activity, LCD Module ON ADC ON, ERM OFF ADC ON, ERM ON
0.2 1
0.4 2
Value may be exceeded with unusual Hardware Option setting Measured with external clock. Add 100 A at 4 MHz, 115 A at 10 MHz for operation on typical quartz with SR3.XTAL = 0 (Oscillator RUN mode).
1) Typical values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested.
2) 3)
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PRELIMINARY DATA SHEET
CDC1607F-E
Table 3-3: UVSS = HVSS1 = HVSS2 = AVSS = 0 V, 4.5 V < VDD = AVDD = UVDD < 5.5 V, 4.75 V < HVDD1 = HVDD2 < 5.25 V, TCASE = -40 C to +105 C, fXTAL = 10 MHz Symbol AIDDq UIDDq EIDDq HIDDq Parameter Quiescent Supply Current Pin Na. AVDD UVDD EVDD1 EVDD2 Sum of all HVDD1 HVDD2 Min. Typ. 1) 1 1 1 1 Max. 10 10 10 20 Unit A A A A Test Conditions ADC and ERM OFF no Output Activity, LCD Module OFF no Output Activity no Output Activity, SM Module OFF
Typical values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested.
1)
3.4. Recommended Quartz Crystal Characteristics
See Chapter 3.4 of document "CDC16xxF-E Automotive Controller - Family User Manual, CDC1605F-E Automotive Controller Specification" (6251-606-1PD).
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CDC1607F-E
4. CPU, RAM, ROM and Banking
phys.addr. 000000 Bottom Boot Config.
PRELIMINARY DATA SHEET
MCM PQFP100
6K RAM
Alternative
log.addr. 0000
Native
log.addr. 000000
001800
Reserved
001900 001A00 001B00 001C00 001D00 001E00 001F00 002000
CAN2-RAM CAN1-RAM CAN0-RAM CAN-Regs Ext. I/O I/O-Reg1 Bank 0 Bank 0
I/O-Reg0
Sector 0, upper 8 KB
004000
Sector 1, 8 KB
006000
Sector 2, 8 KB 7FFF 8000
008000 F800 Boot ROM 010000
Sector 3, 32 KB Boot ROM Sector 4, 64 KB
Bank 1
FFFF 8000 00FFFF 010000
018000
256 KB Flash EEPROM
The device contains a 256 KB Flash EEPROM of the AMD Am29F200BT type (bottom boot configuration). This device exhibits electrical byte program and sector erase functions. Refer to the AMD data sheet for details.
Bank 2
FFFF 8000
Bank 1
Bank 3
FFFF 8000 01FFFF 020000
020000
Sector 5, 64 KB
Bank 4
028000 FFFF 8000
Bank 2
Bank 5
030000 Sector 6, 64 KB FFFF 8000 02FFFF 030000
Bank 6
038000 FFFF 8000
Bank 3
Bank 7
040000 Sector 0, lower 8 KB FFFF 8000 03FFFF 040000
Bank 8
9FFF
Bank 4
041FFF
042000
mirrored Flash EEPROM
FFFFFF
Fig. 4-1: Address Map
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PRELIMINARY DATA SHEET
CDC1607F-E
5. Core Logic
5.1. Control Register CR
The Control Register CR serves to configure the ways by which certain system resources are accessed during operation. The main purpose is to obtain a variable system configuration during IC test. Upon each HIGH transition on the RESETQ pin, internal hardware reads data from the address location 00FFF3h and stores it to the CR. The state of the TEST and ESTOPCLK pins at this timepoint specifies which program storage source is accessed for this read: Table 5-1: Control byte source 1 TEST 0 or NC 1 Control byte source x internal BOOT ROM (standard for stand-alone operation) external, via multifunction pins in Bus mode (for test purposes only) 1 x normal mode normal mode MFM Multifunction Pin Mode (Tables 5-2 and 5-3)
Table 5-2: TSTTOG and MFM usage in mask ROM parts TSTTOG 0 1 MFM 0 0 TEST pin x 0 Multifunction Pins Bus mode Bus mode
Table 5-3: TSTTOG, EBTRI and MFM usage in Flash and EMU parts TSTTOG 0 1 EBT RI x x MFM TEST pin x 0 1 x 0 1 1 x Multifunction Pins Bus mode Bus mode normal mode normal mode Emulator mode Flash mode TestROM (Table 5-4) FLASH EEPROM (Table 5-5) Internal ROM (Tables 5-4 and 5-5) Emulator Bus Pins Flash mode Flash mode
The system will thus start up according to the configuration defined in address location 00FFF3h, automatically copied to register CR.
0 0
CR
7 6
Control Register
5
x
4
MFM MFM
3
2
1
IRAM IRAM
0
ICPU ICPU ROM Emu Res
r/w RESLNG TSTTOG
TSTROM IROM FLASH IROM
r/w RESLNG TSTTOG EBTRI
Value of 00FFF3h
RESLNG Reset Pulse Length r/w1: Pulse length is 16/FXTAL r/w0: Pulse length is 4096/FXTAL This bit specifies the length of the reset pulse which is output at pin RESETQ following an internal reset. If pin TEST is 1 the first reset after power on is short. The following resets are as programmed by RESLNG. If pin TEST is 0, all resets are long. TSTTOG TEST Pin Toggle (Tables 5-2 and 5-3) This bit is used for test purposes only. If TSTTOG is true in IC active mode, pin TEST can toggle the multifunction pins between Bus mode and normal mode. EBTRI Emulator Data Bus Tristate (Table 5-3)
TSTROM FLASH IROM
Table 5-4: TSTROM and IROM usage in mask ROM parts TSTROM 1 0 x 0 IROM 1 selected program storage internal ROM internal TestROM external via Multifunction pins in Bus mode
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CDC1607F-E
Table 5-5: FLASH and IROM usage in FLASH and EMU parts FLASH 1 0 x 0 IROM 1 selected program storage internal FLASH EEPROM resp. Emulator Bus internal BOOT ROM external via Multifunction pins in Bus mode
PRELIMINARY DATA SHEET
IRAM r/w1: r/w0: ICPU r/w1: r/w0:
Internal RAM Enable internal RAM. Disable internal RAM. Internal CPU Enable internal CPU. Disable internal CPU.
Table 5-6: Some commonly used settings for address location 00FFF3h. A copy is automatically transferred to the CR during IC start-up. Code FFh ABh DFh TEST Pin 0 1 0 Operation Mode Stand-alone with internal ROM or Flash External program storage connected to multifunction pins in Bus mode Emulator mode (CPGA177 package)
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PRELIMINARY DATA SHEET
CDC1607F-E
6. Hardware Options
6.1. Functional Description
Hardware Options are available in several areas to adapt the IC function to the host system requirements: - clock signal selection for most of the peripheral modules from fosc to fosc/217 plus some internal signals. (see table in Chapter Hardware Options of document "CDC16xxF-E Automotive Controller - Family
User Manual, CDC1605F-E Automotive Controller Specification" (6251-606-1PD))
- interrupt source selection for interrupt inputs 5, 6, 7, 13, 14 and 15 - Special Out signal selection for some U and H-ports - Rx/Tx polarity selection for SPI and UART modules - U-port Port Slow Mode selection Hardware Option setting requires two steps: 1. selection is done by programming dedicated address locations with the desired options' code 2. activation is done by a read access to these dedicated address locations at least once after each reset. Address locations 00FFB8h through 00FFBFh do not allow random setting. Their respective Hardware Options are hard-wired and can only be altered by changing a production mask for this IC. By default, the Port Slow Option is set for all U-Ports, with the exception of U1.0 to U1.3 (Port Fast Option is set). The Watchdog and Clock Monitor are activated via software by default. Future mask ROM derivatives of this IC will not require (but will tolerate) activation of option settings by read accesses, as the ROM as well as the options will be hard-wired. Instead, the manufacturer will automatically process the setting of the dedicated address locations, as given in the ROM code file, to set the required mask changes. To ensure compatible option settings in this IC and mask ROM derivatives when run with the same ROM code, it is recommended to always read locations 00FFA0h through 00FFC3h directly after reset. Please note that the non-programmable locations 00FFB8h through 00FFBFh may not be compatible within this IC and the mask ROM derivative.
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CDC1607F-E
7. Differences
This chapter describes differences of this document to predecessor document "CDC1607F-E Automotive Controller", of March 31, 2003, 6251-608-2AI. # 1 Section 1. Introduction Description
PRELIMINARY DATA SHEET
1.1. Features, Table 1-1: CDC16xxF Family Feature List, page 4: Interrupt Controller expanding NMI: "16 priority levels" changed into "15 priority levels" and no. of "Port Wake-Up Inputs including Slope / Level Selection" added. 1.1. Features, Table 1-1: CDC16xxF Family Feature List, page 6: Temperature Range, CDC1605F-E EMU: "Tcase: -40 C to +105 C" changed into "Tcase: 0 to +70 C".
2
2. Package and Pins
2.1. Package Outline Dimensions, Fig. 2-1: changed. 2.3. External Components: Fig. 2-3: "Recommended external supply and quartz connection for low electromagnetic interference (EMI)" corrected.
3
3. Electrical Data
3.1. Absolute Maximum Ratings: Revised introduction. 3.2. Recommended Operating Conditions: Revised Introduction; Tj removed. 3.3. Characteristics: Heading revised and reference added, Table 3-3: footnote 6 and some values revised, Rthjc, Rthja: Test Conditions added, AIDDa: Test Conditions changed. 3.4. Recommended Quartz Crystal Characteristics: Table 3-4 removed and reference added instead.
4 5
6. Core Logic 7. Differences
5.1. Control Register CR: The description of RESLNG corrected. Updated
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PRELIMINARY DATA SHEET
CDC1607F-E
Micronas
May 26, 2004; 6251-608-1PD
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CDC1607F-E
8. Data Sheet History
1. Advance Information: "CDC1607F-E Automotive Controller Specification", Feb. 17, 2003, 6251-608-1AI. First release of the advance information. Originally created for the HW version CDC1607F-E1. 2. Advance Information: "CDC1607F-E Automotive Controller Specification", March 31, 2003, 6251-608-2AI. Second release of the advance information. Originally created for the HW version CDC1607F-E2. 3. Preliminary Datasheet: "CDC1607F-E Automotive Controller", May 26, 2004, 6251-608-1PD. First release of the preliminary datasheet. Originally created for the HW version CDC1607F-E2.
PRELIMINARY DATA SHEET
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-608-1PD
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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